"Dirty" bit: set to 1 by CPU if there was a write access to that page. Page attribute table since Pentium III, must be zero for older CPUs.PDE structures in normal mode, PSE mode, and PSE-36 mode are as follows: The PS bit (bit 7) in the Page Directory Entry (PDE) denotes whether this entry refers to a page table (that describes 1024 4-KiB pages) or one 4 MB page. This allows a large page to be located in 36 bit address space. If newer PSE-36 capability is available on the CPU, as checked using the CPUID instruction, then 4 more bits, in addition to the 10 bits used in PSE, are used inside a page directory entry pointing to a large page. As long the processor (as indicated by cpuid) and chipset support PSE-36, enabling PSE alone (by setting bit 4, PSE, of the system register CR4) allows the use of large 4 MB pages (in the 64 GB range) along with normal 4 KB pages (which are however restricted to the 4 GB range). Activation and useĪs far as activating PSE-36, there isn't however a separate bit from the one that turns on PSE. (This is a different bit from plain PSE support, which is indicated by bit 3 in the same register). Support for PSE-36 is indicated by EDX bit 17 (counting from 0) in the cpuid result for feature bits.
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